Senior FPGA Design Engineer

We are seeking an experienced Senior FPGA Design Engineer who will be responsible for designing, bringing-up, debugging, and verifying FPGA-based systems. The ideal candidate should have excellent expertise in Verilog/SystemVerilog design, using C/C++, Matlab, and Python for modeling purposes.

Responsibilities:

1) Design, implement, and debug FPGA-based systems using Verilog/SystemVerilog.
2) Synthesis, place, and route FPGA designs.
3) Perform static timing analysis to ensure timing closure.
4) Conduct simulation using Xsim and VCS.
5) Document design intent and share it with stakeholders.
6) Perform bring-up, debug, and validation of designs to achieve functional and performance goals.
7) Work closely with cross-functional teams to ensure successful project completion.
8) Possess broad knowledge in Bus Protocols such as AMBA and peripheral interfaces such as SPI/I2C.
9) Strong base in Wireless Communication Systems, Digital Communication Concepts would be an added advantage.

Requirements:
1) Bachelor’s or Master's Degree in Electrical/Electronic Engineering or Computer Engineering.
2) 5+ years of proven experience in FPGA design.
3) Excellent knowledge of Verilog/SystemVerilog, and modeling experience using C/C++, Matlab, and Python.
4) Must be well-versed with synthesis, place and route, and static timing analysis.
5) Must have experience in simulation using Xsim and VCS.
6) DSP experience will be helpful.
7) Must possess excellent communication and teamwork skills.
If you meet these qualifications, please submit your resume and cover letter. We are an equal opportunity employer and welcome candidates from diverse backgrounds.

Contact Email -- [email protected]; [email protected]